Typically, in a prior art microprocessor based computer system having a plurality of components such as a microprocessor, a memory, and peripheral devices, it is necessary to exchange information among these components. For instance, the microprocessor may access the memory for reading data from or writing data to the memory. In addition, the memory may be accessed by a peripheral device such as a disk drive for data transfer. The information exchange in such a computer system is typically accomplished via a bus that is coupled to all the components in the computer system.
However, in such a prior computer system, each component is typically operating under an independent clock. In this case, each of the components in the computer system is generally unaware of the timing behavior of the others. Therefore, data transfer between the components in the computer system requires an interface that can synchronize the data transferred from the sender's clock to the receiver's clock. The interface must also be able to synchronize any return signal from the receiver with the sender's clock signal.
Typically, in one prior art interface between two components, a synchronizer is required to perform a handshake operation. FIG. 1 illustrates the use of the synchronizer for the handshake operation for the data transfer. In FIG. 1, a sender 1 is shown to represent the component in the computer system that is transferring data out. A receiver 2 represents the component that receives the data being transferred from sender 1. A synchronizer 3 is coupled between sender 1 and receiver 2. The data being transferred is first sent from sender 1 to synchronizer 3 at the sender's clock. The data is then synchronized to the receiver's clock at synchronizer 3 and fetched by receiver 2 at the receiver's clock. Synchronizer 3 receivers the receiver's clock via line 5.
Another synchronizer 4 is also coupled between sender 1 and receiver 2 to form a return path between sender 1 and receiver 2. When the data transfer is completed, receiver 2 sends an acknowledge signal at receiver's clock to synchronizer 4. The acknowledge signal is then synchronized at synchronizer 4 to sender's clock and is fetched by sender 1. Synchronizer 4 receives the sender's clock via line 6.
One disadvantage associated with such arrangement is that the data being transferred to the receiver has to be delayed in the synchronizer in order for the data to be synchronized with the receiver's clock signal. When the data is latched into the synchronizer, the data is held in the synchronizer for at least one clock phase period at the receiver's clock rate in order to assure that the data is received and synchronized. In this case, synchronization penalty is paid that causes much time to be wasted in the data transfer.
Another disadvantage associated with the arrangement is that any data transfer within the computer system has to be accompanied by the handshake operation. This requires additional logic, such as the synchronizer, to accomplish the operation. In this case, the logic of the interface becomes more complicated and more costly.